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DM74S299 3-STATE 8-Bit Universal Shift/Storage Register
August 1986 Revised May 2000
DM74S299 3-STATE 8-Bit Universal Shift/Storage Register
General Description
This Schottky TTL eight-bit universal register features multiplexed inputs/outputs to achieve full eight bit data handling in a single 20-pin package. Two function-select inputs and two output-control inputs can be used to choose the modes of operation listed in the function table. Synchronous parallel loading is accomplished by taking both function-select lines, S0 and S1, HIGH. This places the 3-STATE outputs in a high-impedance state, which permits data that is applied on the input/output lines to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. A direct overriding input is provided to clear the register whether the outputs are ENABLED or OFF.
Features
s Multiplexed inputs/outputs provide improved bit density s Four modes of operation: Hold (Store) Shift Right Shift Left Load Data
s 3-STATE outputs drive bus lines directly s Can be cascaded for N-bit word lengths s Operates with outputs enabled or at high Z s Guaranteed shift (clock) frequency 50 MHz s Typical power dissipation 700 mW
Ordering Code:
Order Number DM74S299N Package Number N20A Package Description 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
(c) 2000 Fairchild Semiconductor Corporation
DS006485
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DM74S299
Function Table
Inputs Mode Function Clear Select S1 Clear Hold Shift Right Shift Left Load L L H H H H H H H X L L X L L H H H Output Control Clock Serial SL SR X X X L X X X X X X H L X X X X X H L X X X L L QA0 QA0 H L QBn QBn a L L L L L L L L L L L L QG0 QG0 QFn QFn QHn QHn g L L L L L L A/QA B/QB C/QC D/QD E/QE F/QF G/QG H/QH QA QH Inputs/Outputs Outputs
G2 G1 S0 (Note 1) (Note 1) L X L X H H L L H L L L L L L L L X L L L L L L L L X
QB0 QC0 QD0 QE0 QF0 QB0 QC0 QD0 QE0 QF0 QAn QBn QCn QDn QEn QAn QBn QCn QDn QEn QCn QDn QEn QFn QGn QCn QDn QEn QFn QGn b c d e f
QH0 QA0 QH0 QH0 QA0 QH0 QGn QGn H L h H QGn L QGn QBn H QBn a L h
a...h = The level of the steady-state input at inputs A through H, respectively. These data are loaded into the flip-flops while the flip-flop outputs are isolated from the input/output terminals. H = HIGH Level L = LOW Logic Level X = Either LOW or HIGH Logic Level QA0...QH0 = The output logic level of QX before the indicated input conditions were established. QAn...QHn = The output logic level before the active transition () of the clock input. Note 1: When one or both output controls are HIGH the eight input/output terminals are disabled to the high-impedance state; however, sequential operation or clearing of the register is not affected
Logic Diagram
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DM74S299
Absolute Maximum Ratings(Note 2)
Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 5.5V 0C to +70C -65C to +150C
Note 2: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation.
Recommended Operating Conditions
Symbol VCC VIH VIL IOH IOL fCLK fCLK tW Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current (QA thru QH) HIGH Level Output Current (QA, QH) LOW Level Output Current (QA thru QH) HIGH Level Output Current (QA, QH) Clock Frequency (Note 3) Clock Frequency (Note 4) Pulse Width (Note 5) Clock HIGH Clock LOW Clear LOW tSU Setup Time (Note 6)(Note 5)(Note 7) Select Data HIGH Data LOW tH tREL TA Hold Time (Note 5)(Note 7) Clear Release Time (Note 5) Free Air Operating Temperature 0 0 10 10 10 15 7 5 5 10 0 70 ns ns C ns ns 70 60 Parameter Min 4.75 2 0.8 -6.5 -0.5 20 6 50 40 Nom 5 Max 5.25 Units V V V mA mA MHz MHz
Note 3: CL = 15 pF, RL = 280, TA = 25C and VCC = 5V. Note 4: CL = 50 pF, RL = 280, TA = 25C and VCC = 5V. Note 5: TA = 25C and VCC = 5V. Note 6: The symbol () indicates the rising edge of the clock pulse is used for reference. Note 7: Data includes the two serial inputs and the eight input/output data lines.
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DM74S299
Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted) Symbol VI VOH VOL II IIH Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage Input Current @ Max Input Voltage HIGH Level Input Current IIL LOW Level Input Current IOZH Off-State Output Current with HIGH Level Output Voltage Applied (QA thru QH) IOZL Off-State Output Current with LOW Level Output Voltage Applied (QA thru QH) IOS Short Circuit Output Current (QA thru QH) Short Circuit Output Current (QA, QH) ICC Supply Current
Note 8: TA = 25C and VCC = 5V. Note 9: All typicals are at VCC = 5V, TA = 25C. Note 10: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Conditions VCC = Min, II = -18 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIH = Min, VIL = Max VCC = Max, VI = 5.5V VCC = Max VI = 2.7V VCC = Max VI = 0.5V VCC = Max, VO = 2.4V VIH = Min, VIL = Max VCC = Max, VO = 0.5V VIH = Min, VIL = Max VCC = Max (Note 10) VCC = Max (Note 10) VCC = Max A thru H, S0, S1 Any Other Clock, Clear S0, S1 Other QA thru QH QA, QH
Min
Typ (Note 8) 3.2 3.4
Max -1.2
Units V V
2.4 2.7
0.5 1 100
V mA A
50 -2 -0.5 -0.25 100 A mA
-250
A
-40 -20 140
-100 mA -100 225 mA
Switching Characteristics
at VCC = 5V and TA = 25C (See Section 1 for Test Waveforms and Output Load) RL = 280 (Note 12) Symbol Parameter From (Input) To (Output) fMAX tPLH tPHL tPLH tPHL tPHL tPHL Maximum Clock Frequency Propagation Delay Time LOW-to-HIGH Level Output (Note 12) Propagation Delay Time HIGH-to-LOW Level Output (Note 12) Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time HIGH-to-LOW Level Output (Note 12) Propagation Delay Time HIGH-to-LOW Level Output tPZH tPZL tPHZ tPLZ Output Enable Time to HIGH Level Output Output Enable Time to LOW Level Output G1, G2 to QA thru QH G1, G2 to QA thru QH 12 12 Clear to QA thru QH Clear to QA or QH 21 Clock to QA thru QH Clock to QA thru QH Clock to QA or QH (Note 13) Clock to QA or QH CL = 15 pF Min 50 20 20 Max CL = 50 pF Min 40 22 23 21 21 24 24 18 18 Max MHz ns ns ns ns ns ns ns ns ns ns Units
Output Disable Time to HIGH Level Output (Note 11) G1, G2 to QA thru QH Output Disable Time to LOW Level Output (Note 11) G1, G2 to QA thru QH
Note 11: CL = 5 pF. Note 12: RL = 1K for delays measured to QA and QH. Note 13: For testing fMAX all outputs are loaded simultaneously.
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DM74S299 3-STATE 8-Bit Universal Shift/Storage Register
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 5 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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